1. Field of the Invention
The present invention relates to a semiconductor timer, particularly to a timer circuit formed on a metal oxide semiconductor (MOS) integrated circuit.
2. Description of the Prior Art
In certain MOS integrated circuits, it is necessary to provide a timer circuit which can set a long time interval. For example, an electrically erasable and programmable read only memory (EEPROM) in general requires timer circuits having a time interval of about 10 to 20 msec for erasing and writing operations. According to the prior art, since such a time interval is produced by a time delay of a continuously charged or discharged CR circuit, a capacitor having a relatively high capacitance, for example, about 5600 pF, is required. Such a capacitor cannot be formed from a semiconductor, so an external capacitor having a very high capacitance is attached to the integrated circuit. However, this requires the integrated citcuit to have an additional connecting pin, and adds to the manufacturing process.
Furthermore, when the EEPROM functions include automatically erasing, writing, and performing verification, timer circuits or delay circuits having a time interval of about 3 to 5 msec are required to produce each control pulse. According to the prior art, since such timer circuits or delay circuits are formed from a continuously charged or discharged CR circuit consisting of a depletion mode transistor and a MOS capacitor in the MOS integrated circuit, the sizes of the depletion mode transistor and MOS capacitor are very large. Particularly, the size of the MOS capacitor is extremely large. For example, a timer circuit having a time interval of 3 msec requires a depletion mode transistor having a size of about W/L=5 .mu.m/500 .mu.m and a MOS capacitor having a size of about W/L=500 .mu.m/500 .mu.m, where W indicates the channel width and L indicates the channel length of a MOS transistor or capacitor.